Literature Map

An eight-transistor (8T) SRAM cell is proposed to improve variability tolerance and low-voltage operation in high-speed SRAM caches. No need for secondary or dynamic power supplies. The proposed 8T solution is demonstrated in a high-performance 32 kb subarray designed in 65 nm PD-SOI (Partially-Depleted Silicon-On-Insulator) CMOS that operates at 5.3 GHz at 1.2 V and 295 MHz at 0.41 V.

A reconfigurable 2’s-complement and sign-magnitude scheme integrated within a versatile-format CIM macro supporting MX, LNS, FP, and INT for MAC operations.
Stats: 16nm 72kb gain-cell array, energy efficiency of 120.5TFLOPS/W and throughput density of 3.18 TOPS/mm2 in MXINT8 mode.

Queueing theoretic models can guide design trade-offs in systems targeting tail latency, not just average performance.

Software techniques that tolerate latency variability are vital to building responsive large-scale web services.